A Fast Crc Implementation on Fpga Using a Pipelined Architecture for the Polynomial Division

A Fast CRC Implementation on FPGA Using a Pipelined Edifice for the Polynomial Diskey Fabrice MONTEIRO, Abbas DANDACHE, Amine M’SIR,Bernard LEPLEY LICM, University of Metz, SUPELEC, Rue Edouard Belin, 57078 Metz Cedex phone: +33(0)3875473 11, fax: +33(0)387547301, email: fabrice. [email protected] org ABSTRACT The CRC falsity defiance is a very niggardly discharge on telecommunication applications. The extrication towards increasing axioms admonishs requires further and further sofisticated instrumentations. In this disquisition, we introduce a arrangement to instrument the CRC discharge inveteadmonish on a pipeline constituency for the polynomial dissolution.It reforms very cogently the urge work, allowing axioms admonishs from 1 Gbits/s to 4 Gbits/s on FPGA instrumentions, according to the analogousisation roll (8 to 32 bits). 1 INTRODUCTION The CRC (Cyclic Redundancy Checking) codes are used in a lot of telecommunication applications. They are used in the inner layers of protocols such as Ethernet, X25, FDDI and ATM (AAL5). However, on modem networks, the claim for increasing axioms admonishs (balance 1 Gbit/s) is elucidation the businesss on work very violent. Indeed, the urge progress (remarkable clock admonishs) due to the technological extrication is unable to fit the claim.Consequently, new edifices must be bequeathed. Targetting the applications to an FPGA invention is an effect for this disquisition, as it allows low-cost contrivances. The weak and obvious serial instrumentation is a refined hardware instrumentation of the CRC algorithm. Unfortunatly, on an FPGA instrumentation after a conjuncture maximal clock reckon of 250 MHz, maximal axioms admonish is poor to 250 Mbits/s is the best fact. Remarkable axioms admonishs can merely be obtained through analogousisation. Some analogous edifices possess been proposed in the late to harangue the claim for violent axioms throughput [ 1][2].The ocean collection is usually to word the astride increasing area balancehead conjuncture neat the urge work. In this disquisition, we introduce a analogous mode for the polynomial diskey inveteadmonish on a pipeline constituency. The analogousisation can be led to any roll and is merely lim- ited by the area business set on the contrivance. The axioms throughput is closely instantly linked to the analogousisation roll, as the maximal clock admonish is not very perceptive to it. 2 PRINCIPLE The polynomial diskey is the indispensable action of the CRC applications.The serial instrumentation of the diskey is likenessn in condition 1 for the fact where the polynomial divisor is G ( X ) = Go + G1. X1 + Gz. X2 + G3. X3 = 1 + X + X 3 . As involved formerly, the axioms throughput of this serial instrumentation is completely low. Very violent axioms admonishs can merely be achieved after a conjuncture violent clock frequencies, which in alter can merely be obtained using rather costly technological keys. Parallelisation of axioms ordering is the ocean key to reform the urge work of a tour (or plan) if the clock admonish must reocean low.Pipelining may be used as an cogent analogousisation arrangement when a repeatitive order must be applied on ample volumes of ‘data. Former works possess harangueed the analogousisation collection in ample claiming computational applications, especially in arithmetic (eg. [3][4]) and falsity curb coding tours (eg. [11[21[61). In the serial edifice (condition I), a new axioms bit is inject on each clock cycle. The former cumulated tarryder is simultaneously numerous by X and disjoined by G(z) (where G(z) is the polynomial divisor). On P Condition I : Serial polynomial diskey for G ( X ) = 1 -tX + X 3 -7803-7057-0/01/$10. 00 02001 IEEE. 1231 successive clock cycle , P bits are injected and P successive multitudinousness and dissolutions are manufactured. The present formula (akin to the model of condition 1) describes the action manufactured on one clock cycle. 0 T = [ o o 1 !]=[n Gz 0 1 o 1 1 Go GI 0 i ] 0 3 RESULTS This edifice possess been instrumented on FPGA inventions of the FLEXlOKE ALTERA extraction. These inventions possess their maximal clock reckon poor to 250 MHz. The edifice was tested on the generating polynomials of consultation 1. The ends in consultation 2 were obtained on FPGA inventions of the FLEXlOKE ALTERA extraction.The edifice tested in these models instruments a abundantly actional CRC checker. The synchronisation signals to transcribe and unravel axioms relatively on input and ouput are abundantly instrumented. The body was produced using Synplify 5. 3 and MaxPlus11 10. 0. The edifice was tested for 3 divergent rolls of paralelism on 6 divergents trutination divisor polynomials. It can be noticed that G17(z) is used on ethernet, FDDI and AALS-ATM, conjuncture G14(z) is the trutination polynomial for the X2. 5 protocol. The clock admonishs must be compared to the violentest reckon (250 MHz) that can be manufactured on FLEXlOKE inventions.The “IC” demonstration media “logical cells” and is an demonstration of the area hitherening. The ends must be compared to those obtained in [SI. A axioms admonish of 160 Mbits/s was obtained on an ALTERA FLEXIOK invention (max. clock admonish of 125 MHz), on a 32-bit analogous CRC runtime-configurable instrumentation of the decoder, inveteadmonish on the use of analogous combi- A pipeline constituency can be bequeathed by the instrumentation of P successive multitudinousnesss and dissolutions. However, to restrain the clock admonish violent, the P actions should not be produced in a solitary combinatorial stop. Thus, the measures of the P-multiplingldivising stop must be disjoined by memorials.This is the basic purpose of the pipeline constituency. Each of the P analogous bits of an input must be injected in their relative pipeline measure. therefore, they must be injected on divergent clock cycles. This may be produced if the bits are advanced in a remove-record constituency and (cf. the remove record road between [ d i n o ,. .. , [douto, ... ,doutp-l] in the condition 2, after a conjuncture P = 8 in this model and G ( X ) = 1 + X + X 3 . The action manufactured when passing from the measure k + l to the measure k of the pipeline (k>O) is feeling in the present formula, where G ( X ) = 1 + X + X 3 as it is in condition 2. ith Ri,J= 0 wheni + j > p - 1. The P bits of an input are ordered in P clock cycles. At each clock cycle, the end of the ordering of P bits is conducive at the output of the pipeline constituency. This end (the tarryder of the P bits disjoined by G(z) must be cumulated in the [ROO, ROZ] ROI, record using a reiterated mode, concordant to the contrivance of the serial edifice of condition 1. The cumulated tarryder at era t must be numerous by X p and then disjoined by G(x). Then, the new peculiar tarryder future out of the pipeline constituency can be cumulated. This order is describet in the present formula. Ro,o,ROJ,R0,Sltfl = [Ro,o,RO,l,R0,zIt * M +[Ri,o, Ri,i, Rl,z]t * T f [Do,P-l, 0,Olt natorial stop for the polynomial diskey as introduceed in [ 11. The bring-about obtained on the 32-bit analogous edifice is after a conjuncturein 16 and 30 eras, that is, 8 to 1. 5 eras using the identical technology (cf. consultation 2). For any union of the contrivance parametres, the latency is alway similar to P clock cycles where P denotes the analogousisation roll. It can be noticed that for abandoned a maximal polynomial divisor quality, the area hitherening (reckon of logic cells ) is closely proportional to the analogousisation roll of the edifice.Furthermore, the ends likeness that a ample extension of the analogousisation roll can be produced after a conjuncture a sedate reduce of maximal clock reckon. The censorious road is due to the M matrix. The perplexity of this matrix depends on the choosen polynomial (reckon and position of the non-zero provisions in the polynomial). It to-boot depends on the analogousisation 1232 roll, but not linearly. Actually, a violenter analogousisation roll can guide to a hither abstruse matrix.